1. Field of the Invention
The present invention relates to a non-volatile memory device and a method of driving the same, and more particularly, to a non-volatile memory device in which initial setting data is read from a memory cell array, and a method of driving the same.
2. Description of the Related Art
A flash memory, which is a popular type of non-volatile memory, is a memory device from which data can be electrically deleted and to which data can be electrically written. Flash memory not only consumes less power than storage media based on a magnetic disc memory, but also requires a relatively short access time, similar to hard discs.
Flash memory is categorized into a NOR type flash memory and a NAND type flash memory, depending on how cells and bit lines are connected. The NOR type flash memory has a structure in which two or more cell transistors are connected in parallel to each bit line, and stores data using a channel hot electron method and deletes data using a Fowler-Nordheim (F-N) tunneling method. The NAND type flash memory has a structure in which two or more cell transistors are connected in series to each bit line, and stores data or deletes data using the F-N tunneling method. In general, the NOR type flash memory consumes a large amount of current and is difficult to highly integrate, but operates at very high speeds. In contrast, the NAND type flash memory uses less cell current than the NOR type flash memory, and is easier to highly integrate.
FIG. 1A is a circuit diagram of a memory cell structure included in a conventional NAND type flash memory. FIG. 1A illustrates word lines WL11 through WL14 and memory cells M11 through M14. The memory cells M11 through M14 form a string structure together with selection transistors ST1 and ST2, and are connected in series between a bit line BL and a ground voltage source VSS. Since the NAND type flash memory uses a small amount of cell current, all memory cells connected to one word line are programmed during a single programming operation.
FIG. 1B is a circuit diagram of a memory cell structure included in a conventional NOR type flash memory. Referring to FIG. 1B, memory cells M21 through M26 are connected between a bit line BL1 (or BL2) and each source line CSL. Since the NOR type flash memory consumes a large amount of current in order to perform a programming operation, a limited number of memory cells are programmed during a single programming operation.
In general, a memory cell array included in a memory device may include a main cell that stores data, and a redundant cell that replaces the main cell when a defect occurs in the main cell. The memory device may further include a fuse circuit for storing the address of a defective cell. The fuse circuit senses when an address received from the outside is a defective address, and replaces the address of a defective cell with the address of a redundant cell.
The fuse circuit stores not only address information for repairing a defective cell, but also information for setting other operating environments when the memory device is powered on. For example, initial setting data, used to set the operating environment of the memory device, may control a DC voltage related to programming a memory device, or reading or erasing data from a memory device.
When the fuse circuit is set to store initial setting data, it is difficult to reprogram the fuse circuit once it is programmed according to a specific manner. It is possible to improve the flexibility of the operating environment of the memory device by reprogramming the initial setting data stored in the memory cell array, which may be done according to a method of storing initial setting data in a memory cell array.
FIG. 2 is a block diagram of a memory cell array 10 with bit lines, and a page buffer unit 20. Referring to FIG. 2, the memory cell array 10 includes one or more blocks Block0 through Blockn, and may have a structure in which multiple pairs of even and odd bit lines BLe and BLo are arranged. The page buffer unit 20 includes multiple page buffers, which are electrically connected to respective pairs of the bit lines BLe and BLo. A page, which is a unit in which programming or data reading is performed in a flash memory, is generally 512 bytes long or 2 k bytes long. When the size of each page is 2 k bytes, for example, page buffers of 2 k bytes are arranged for the page.
FIG. 3 is a block diagram of a memory cell array with a redundant cell array 40, and first and second page buffer units 50 and 60. The memory cell array may include a main cell array 30 and the corresponding redundant cell array 40. For example, the redundant cell array 40 is used to replace “fail” columns of the main cell array 30.
The first page buffer unit 50 corresponding to the main cell array 30 includes multiple page buffers. The page buffers of the first page buffer unit 50 are electrically connected to respective bit lines of the main cell array 30. Also, the second buffer unit 60 corresponding to the redundant cell array 40 includes multiple page buffers. The page buffers of the second page buffer unit 60 are electrically connected to respective bit lines of the redundant cell array 40.
Referring to FIG. 3, the bit lines are arranged in the memory cell array, and a “fail” column may occur in some of them, for example, due to a cut in the bit lines or short circuiting between the bit lines during a manufacturing process. The “fail” column is replaced with a redundant column through a repairing process. According to the repairing process, when a memory device (not shown) is powered on, defective addresses (corresponding to “fail” columns) are read from the main cell array 30 and stored in a predetermined region. Thereafter, when part of the columns input by a user during a programming operation, a read operation, or an erasing operation includes a defective address, the defective column is replaced with a redundant column. FIG. 3 illustrates a repairing process in which “fail” columns occurring in the main cell array 30 are replaced with redundant columns in units of two page buffers. For example, two page buffers 51 corresponding to the columns having defective bit lines are replaced with two page buffers 61 corresponding to two redundant columns.
As described above, when a conventional non-volatile memory device is powered on, an initial read operation is performed to read initial setting data from a memory cell array, and an operating environment of the memory device is set based on the initial setting data. However, as described above, the initial setting data is read before a repairing operation is performed. That is, the initial setting data is read from the memory cell array, which may include “fail” columns. Accordingly, the read initial setting data may include errors, in which case it is likely that the memory device cannot be set to a predetermined operating mode. Therefore, there is a need for preventing initial setting data, which is read from the memory device during an initial read operation, from being invalid.